1. Field of the Invention
The present invention relates to an imaging device, such as a CMOS image sensor (CIS). The invention particularly relates to an imaging device capable of improving desired pixel characteristics, for example, the sensitivity and the amount of accumulated electric charge (Qs), even when the imaging device is formed of a large number of miniaturized pixels.
2. Description of the Related Art
The invention further relates to a method and an apparatus for reading electric charge from the imaging device.
The invention further relates to a method and an apparatus for performing demosaicing on the imaging device.
The invention further relates to an imaging apparatus including the imaging device described above.
In recent CMOS image sensors and other similar imaging devices, a larger number of pixels are formed in a predetermined region to achieve higher definition images, and miniaturization is underway to this end.
When the size of each pixel in an imaging device is miniaturized to, for example, 2 μm or smaller, it has been becoming difficult to provide desired pixel characteristics. In particular, the sensitivity and the amount of accumulated electric charge (Qs) are greatly subject to a physical (spatial) constraint of reduction in pixel size, that is, the above two characteristics and the pixel size are tradeoffs. That is, since reduction in size of a pixel reduces the amount of light incident on the pixel and accumulated in a short period, the sensitivity and Qs decrease. In particular, the sensitivity is more significantly affected. The reason for this will be described later.
To prevent the decrease in Qs and sensitivity due to the reduction in pixel size, the structure of an imaging device and a light collection structure have been optimized (see JP-A-2006-157953 and WO 2006/039486A2, for example).
However, recent miniaturization and other technologies have made it possible to reduce the pixel size to the extent that it approaches the level of the wavelength of light, and the resultant decrease in the amount of light itself incident on (traveling into) a pixel causes improvement in sensitivity characteristics using the existing methods to approach a limit.
An existing light collection structure for improving the efficiency of collecting light into a photodiode, for example, an on-chip lens (OCL), increases the opening area of a pixel to a largest possible value in order to maximize the amount of light incident on (traveling into) the pixel (see JP-A-2008-99073 and JP-A-2006-54276, for example).
That is, the methods described in JP-A-2008-99073 and JP-A-2006-54276 achieve reduction in the area in a pixel that is occupied by wiring lines and sharing between pixels having the same pixel size, that is, reduction in the number of in-pixel wiring lines for reading data and the number of transistors to be used.
Further, to maximize the amount of light itself incident on a photodiode, a structure that allows an inoperative area between OCLs to be reduced in size has been attempted.
An example of related art will be described in detail with reference to the accompanying drawings.
FIG. 1A schematically shows how RGB (red, green, and blue) pixels are arranged in a Bayer layout of related art.
In the arrangement based on a Bayer layout, an RG row in which a red R pixel and a green Gr pixel are alternately disposed and a GB row in which a green Gb pixel and a blue B pixel are alternately disposed are disposed next to each other.
The pixel configuration in FIG. 1A shows that there is no correlation between the Gr and Gb pixels in the horizontal direction.
FIG. 1B shows the arrangement of four adjacent pixels among the RGB pixels in the Bayer layout illustrated in FIG. 1A.
FIGS. 1C to 1E illustrate spatial frequency characteristics of the green, red, and blue components, respectively. It is shown that the spatial frequency characteristics of the red and blue components are inferior to that of the green component.
FIGS. 2A and 2B show the pixel configuration in FIG. 1A in a more practical form.
FIG. 2A is a partial plan view, and FIG. 2B is an enlarged view showing part of FIG. 2A.
Each open dotted-line circle represents an on-chip lens (OCL) or a light collection structure.
The rectangles that surround the R, B, Gr, and Gb pixels represent RGB color filters (CFs) in the arrangement based on the Bayer scheme.
The CFs and the OCLs or light collection structures are formed on the pixels.
A floating diffusion (FD) section indicated by a rectangle divided into four is disposed at the center of a set of B, R, Gr, and Gb pixels. That is, the number of in-pixel wiring lines is reduced by an inter-pixel sharing method using vertical and horizontal wiring lines for connecting adjacent pixels, for example, a sharing method using FD (floating diffusion) sections.
As described above, the sharing method is an inter-pixel sharing method in which an FD section is shared.
FIG. 2C shows how to use four adjacent pixels to achieve inter-pixel sharing.